In the field of semiconductor memory devices, attention has been focused on the three-dimensional stacked memory. Relatively free from the limitation of resolution in lithography technology, the three-dimensional stacked memory can increase the bit density. In an example of such a three-dimensional stacked memory, MONOS memory strings are arranged in a two-dimensional matrix configuration. The MONOS memory string includes a columnar semiconductor pillar. The MONOS memory string further includes a tunnel insulating layer, a charge trap layer, and a block insulating layer stacked so as to cover the side surface of the semiconductor pillar. The MONOS memory string further includes a plurality of plate-shaped electrodes crossing the semiconductor pillar and provided in the stacking direction with a prescribed spacing. In such a three-dimensional stacked memory, the plate-shaped electrode is shared by the memory strings adjacent in a prescribed direction.
In this structure, to increase the bit density, it is necessary to increase the number of stacked layers, or to increase the density of semiconductor pillars. In the latter approach, thinning of the tunnel insulating layer, the charge trap layer, and the block insulating layer constituting the MONOS cell is important.
However, if the tunnel insulating layer is simply thinned in the MONOS memory, then although writing by the tunnel current becomes easy, data retention will become degraded. Thus, a technique of implementing the tunnel insulating layer as an air gap is proposed.
However, in the three-dimensional stacked memory, if the tunnel insulating layer is simply implemented as an air gap, the semiconductor pillar may undergo deformation such as warpage. As a result, the charge trap layer and the semiconductor pillar may be brought into contact with each other. This may decrease the reliability for e.g. writing characteristics.